Automatic test generation for sequential circuits is a difficult task. Several different techniques are used to accomplish this task. Complete scan testing, for example, transforms the sequential circuit into a combinational circuit by making all the memory elements controllable and observable. However, it may not be possible to design every circuit for complete scan testing and the cost in terms of performance and testing overhead may be prohibitive. Partial scan testing is a more cost-effective alternative in which only a subset of the memory elements are tested thereby reducing delay and area overhead as well as test application time.
A method of partial scan testing was reported by E. Trischler in an article entitled "Incomplete Scan Path with an Automatic Test Generation Methodology" in Proceedings of the International Test Conference, pages 153-162, 1980, where flip-flops were selected based on their testability measure. An improved partial scan test method based on testability analysis is described in an article by M. Abramovici et al entitled "The Best Flip-Flops to Scan" in Proceedings of the International Test Conference, pages 166-173, 1991. A detectability cost based partial scan test method which achieves significantly better results compared to other similar approaches is described in an article by P. S. Parikh et al entitled "A Cost Based Approach to Partial Scan" in Proceedings of the 30th ACM/IEEE Design Automation Conference, pages 255-259, June 1993.
Attempts at selecting partial scan FFs in a manner for aiding an automatic test pattern generation (ATPG) program have been described. The results of such techniques are strongly influenced by the order in which the target faults are chosen and by the decisions made by the test generator. Another type of partial scan test method selects flip-flops in an effort to cut or break all feedback loops such that during testing, the circuit appears as a pipeline or a balanced pipeline. These circuit-transformation techniques allow the use of a combinational test pattern generator for ATPG.
Cheng and Agrawal in an article entitled "A Partial Scan method of Sequential Circuits with Feedback" in IEEE Transactions on Computers, vol. 34, pages 544-548, April 1990 and in U.S. Pat. No. 5,043,986 disclosed that the feedback cycles among flip-flops are mainly responsible for test generation complexity. It is known by those skilled in the art that partial scan circuits with self-loops but without feedback cycles are easier to test than circuits having feedback cycles. A self-loop refers to a situation where the output of a flip-flop, after passing through combinational logic circuits, is fed back as an input to the same flip-flop. The ability to allow self-loops to remain in the partial scan test circuit is particularly attractive since a large number of flip-flops in practical designs include self-loops. Therefore, the scan overhead encountered in partial scan testing of such circuits containing self-loops would be high if it was necessary to break all feedback loops, including self-loops.